1. Field of the Invention
This invention relates to a semiconductor integrated circuit device having a power supply voltage lowering circuit for lowering a power supply voltage from the external and supplying the lowered voltage to an internal circuit, and is particularly suitable for a logic LSI such as a microprocessor or DRAM.
2. Description of the Related Art
In a semiconductor integrated circuit device such as a DRAM, since the withstand voltage of the gate insulative film of a MOS transistor is lowered and the resistance to hot carriers is degraded when it is further miniaturized, it becomes necessary to lower the power supply voltage. However, since the whole system must be changed in order to lower the power supply voltage itself which is supplied to the chip, it becomes a common practice to hold the voltage of the system at 5 V as in the conventional case and use a voltage obtained by lowering the power supply voltage supplied from the exterior in the chip in the case of 16-Mbit DRAM.
On the other hand, in the case of 64-Mbit DRAM, the power supply voltage V.sub.CC for the whole system is lowered to 3.3 V, but the power supply voltage lowering circuit is widely used in the chip. The reason is to make the power consumption as small as possible or enlarge the operation margin of the internal circuit and input characteristic for the power supply voltage V.sub.CC and is different from the demand for the 16-Mbit DRAM, but it is considered that the power supply voltage lowering circuit will be widely used not only in the DRAM but also in the semiconductor integrated circuit device.
As the conventional power supply voltage lowering circuit, a feedback type circuit including a P-channel MOS transistor as shown in FIG. 1 and a source follower type circuit including an N-channel MOS transistor as shown in FIG. 2 are known. The basic construction of the former power supply voltage lowering circuit is described in, for example, 1986 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS pp. 272 and 273, Furuyama et al. "An Experimental 4 Mb CMOS DRAM".
The power supply voltage lowering circuit shown in FIG. 1 creates an internal power supply voltage V.sub.DD by lowering a power supply voltage V.sub.CC supplied from the exterior and includes P-channel MOS transistors T1 to T4, N-channel MOS transistors T5 to T8, and resistors R1, R2. The sources of the MOS transistors T5 and T6 are connected together and the MOS transistors T1 and T2 which are connected in a current mirror configuration are connected between the power supply node V.sub.CC and the respective drains of the MOS transistors T5 and T6. The drain-source paths of the MOS transistors T7, T8 are serially connected between the source common connection node of the MOS transistors T5, T6 and the ground node GND. The drain of the MOS transistor T3 is connected to the drain common connection node of the MOS transistors T2, T6 and the source thereof is connected to the power supply node V.sub.CC. Further, the gate of the MOS transistor T4 is connected to the drain common connection node of the MOS transistors T2, T6 and the source thereof is connected to the power supply node V.sub.CC. The resistors R1 and R2 are serially connected between the drain of the MOS transistor T4 and the ground node GND. The gate of the MOS transistor T5 is connected to the connection node between the resistors R1 and R2 and is applied with a potential V.sub.R created by dividing an output potential V.sub.DD.
The gate of the MOS transistor T6 is applied with a reference potential V.sub.REF and the gates of the MOS transistors T3, T7 are supplied with an operation control signal ACT for determining whether the power supply voltage lowering circuit should be operated or not. The operation control signal ACT is set at a high level when the power supply voltage lowering circuit is operated and is set to a low level when the operation thereof is interrupted, and when the power supply voltage lowering circuit is used in a DRAM, for example, the signal ACT is set at a high level in the operative mode and set at a low level in the standby mode. The gate of the MOS transistor T8 is supplied with a signal VCON for driving the MOS transistor T8 as a constant current source. The signal VCON is a constant potential set at an intermediate level between the power supply potential V.sub.CC and the ground potential GND. The internal power supply potential V.sub.DD obtained by lowering the power supply potential V.sub.CC is derived from the connection node between the drain of the MOS transistor T4 and the resistor R1.
The circuit shown in FIG. 1 keeps the output potential V.sub.DD at a constant level by comparing the potential V.sub.R with the reference potential V.sub.REF in the CMOS current mirror type comparing circuit constructed by the MOS transistors T1, T2, T5 to T8 and controlling the MOS transistor T4 according to the result of comparison. In a case where the internal power supply potential V.sub.DD is lower than a preset potential, that is, when V.sub.R &lt;V.sub.REF, the MOS transistor T4 is set to the ON state to raise the output potential V.sub.DD, and when V.sub.R &gt;V.sub.REF, the MOS transistor T4 is set to the OFF state to lower the output potential V.sub.DD.
FIG. 3 shows the relation between the output potential V.sub.DD of the power supply voltage lowering circuit and the external power supply potential V.sub.CC. In FIG. 3, it is ideal if "V.sub.DD =V.sub.CC " when V.sub.CC &lt;3.5 V as indicated by a one-dot-dash line, but in practice, the driving ability of the P-channel MOS transistor T4 is not so large since the size of the P-channel MOS transistor T4 is limited (when it is made excessively large, the delay time in the feedback loop including the current mirror circuit in the case of "V.sub.CC &gt;3.5 V" becomes too long and the operation becomes unstable) and the potential applied to the gate of the MOS transistor T4 is an output directly derived from the current mirror circuit and is not set at the GND level, and the relation of V.sub.DD &lt;V.sub.CC is obtained as indicated by the solid line. Further, in the feedback type voltage lowering circuit including the P-channel MOS transistor, the feedback operation is effected and the output potential will oscillate in some condition, and therefore, fine adjustment by phase compensation, for example, is required, thereby making the circuit design difficult. In addition, since the feedback time constant is not limitlessly small, it cannot respond to a rapid variation in the internal potential and noise will be generated.
On the other hand, the power supply voltage lowering circuit of FIG. 2 is a source follower type circuit using an N-channel MOS transistor T10. An internal power supply voltage V.sub.DD output from the source of the voltage lowering MOS transistor T10 of N channel type is controlled to V.sub.PP -V.sub.TH (V.sub.TH is a threshold voltage of the N-channel MOS transistor T10) by applying a high potential V.sub.PP to the gate of the MOS transistor T10 and applying an external power supply potential V.sub.CC to the drain thereof. Since the power supply voltage lowering circuit of source follower type using the N-channel MOS transistor T10 has no defects of oscillation and through current which are caused in the feedback type circuit, the MOS transistor size can be made sufficiently large, the response to the internal load is good, and the circuit characteristic is excellent. Further, by dispersedly arranging the N-channel MOS transistor T10 in the chip, degradation in the AC characteristic due to an IR drop caused by a resistance between the V.sub.DD generation circuit and the actual load circuit will not occur and an excellent response characteristic can be attained.
However, the power supply voltage lowering circuit of source follower type has an essential defect that the internal potential will be made significantly higher than an original preset value in a standby state in which almost no load current flows. Further, even in a state other than the standby state, if the load current becomes small, the internal potential tends to rise. Therefore, if the voltage lowering circuit is used in a DRAM, for example, the internal power supply potential has a dependency on the cycle time t.sub.RC, that is, cycle time of RAS and it is not desirable (the internal power supply potential becomes higher as the cycle time becomes longer).
FIG. 4 shows the above state, and since the abscissa indicates the reciprocal of t.sub.RC, "0" on the abscissa indicates the standby state. As is clearly seen from FIG. 4, the potential is set to a potential level significantly higher than an original preset value in the standby state. The above problem can be solved by providing an adequate current path so as to always pass a load current in the standby state between the output terminal of internal power supply potential V.sub.DD and the ground node GND. However, the current required in the standby state is set to as large as several mA since the channel width of the N-channel MOS transistor T10 acting as the voltage lowering circuit is as large as 10.sup.4 .mu.m or more, and therefore, the above measure cannot be taken for the DRAM in which the standby current is required to be suppressed to 100 .mu.A or less.
Of course, when the cycle time becomes longer, the power consumption is reduced (the power consumption varies inversely with the cycle time) and no influence is given to the electric power evaluated in the worst condition of the minimum cycle time, and therefore, a problem that the power consumption increases will not occur. Further, in a device such as a DRAM which is set into the standby state by setting a RAS signal to a high level, even if the internal power supply potential rises in the standby state and VILmax (the, maximum input signal level of an input signal which an input buffer can sense as a high level input signal) rises in the input buffer for R including the P-channel MOS transistors T11, T12 and N-channel MOS transistors T13 to T16 shown in FIG. 5, it is not difficult for the device to be set into the active state and no problem occurs. If the device starts to be operated in response to a RAS signal, a large current is caused to flow in the internal load so that the internal potential will be rapidly lowered to the preset potential and no problem occurs. However, the power supply voltage lowering circuit of source follower type using the N-channel MOS transistor has the following four problems (a) to (d) when it is used in a DRAM.
(a) The device is set into the standby state when RAS is set to a high level, and after a while, the internal power supply potential V.sub.DD starts to rise and VIHmin (the minimum input signal level of an input signal which the input buffer can sense as a high level input signal) of RAS rises. Then, the RAS buffer senses an input signal which has been sensed as a high level signal as a low level signal and the device is set into the active state. As a result, since the internal potential is lowered and VIHmin is lowered again, the input buffer senses RAS as a high level signal and is set into the standby state. Then, after a short period of time, the internal power supply potential V.sub.DD starts to rise and VIHmin of RAS rises. Then, it is set into the active state again. If the operation is repeatedly effected, the oscillation occurs.
(b) In a DRAM having a self-refresh mode, the standby state may be sometimes kept set for a long time in the chip while RAS is kept at a low level. At this time, the internal power supply potential V.sub.DD rises in some cases although RAS is set at the low level. In this case, there occurs a possibility that the self-refresh mode cannot be reset when VIHmin is raised even if RAS is set back to the high level to set the device into a mode from the self-refresh mode.
(c) For example, in a case where RAS, CAS are continuously output for a long time in the active state in the normal read operation, the current consumption in the internal circuit becomes substantially "0" and the internal power supply potential V.sub.DD gradually rises. Then, there occurs a possibility that such a long cycle cannot be interrupted when VIHmin is raised even if RAS is raised to interrupt the long cycle.
(d) In a case where the bit line precharge potential V.sub.BL is created based on the internal potential by using half the internal potential of the chip, for example, the potential V.sub.BL also rises when the standby state is kept for a long time. In this case, since the impedance of the bit line precharge potential generating circuit is not so large, the bit line precharge potential V.sub.BL is kept at a level higher than the preset value for a while after the active state is set, and therefore, the readout margin of the memory cell is reduced and an error may occur.
In any case of the above problems (a) to (d), the above problem will not occur if the RAS input buffer and the bit line precharge potential generating circuit are designed to be driven by an external power supply voltage. However, if they are so designed, it makes no sense to omit the dependency of the input characteristic on the external power supply potential V.sub.CC and the operation margin for the external power supply potential V.sub.CC is reduced accordingly, thereby reducing the effect obtained by using the power supply voltage lowering circuit.
The conventional semiconductor integrated circuit device having, as described above, a power supply voltage lowering circuit of feedback type including a P-channel MOS transistor has a problem that the output potential of the voltage lowering circuit falls below a preset value (ideal value) when a current abruptly flows through the load while the external power supply potential is low. Further, there occurs a problem that the circuit design is difficult and noise is generated. Further, the conventional semiconductor integrated circuit device having a source follower type power supply voltage lowering circuit including an N-channel MOS transistor has a problem that the internal power supply potential is raised to a level significantly higher than an original preset level in the standby state in which almost no load current flows.